Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs

Zhen-Lei Yang; Xiao-Hui Wang; Zhan-Gang Zhang; Jie Liu; Hong Su

doi:10.1088/1674-1137/40/4/046103

Chinese Physics C> 2016, Vol. 40> Issue(4) : 046103 DOI: 10.1088/1674-1137/40/4/046103

Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs

1.
Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China
3.
Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China
4.
Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China

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Abstract：
Embedded RAM blocks(BRAMs) in field programmable gate arrays(FPGAs) are susceptible to single event effects(SEEs) induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes(ECCs), the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed, and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.
- single event effects ,
- flash-based FPGAs ,
- BRAMs ,
- error correcting codes ,
- Hamming codes ,
- BCH codes

References

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Zhen-Lei Yang, Xiao-Hui Wang, Zhan-Gang Zhang, Jie Liu and Hong Su. Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs[J]. Chinese Physics C, 2016, 40(4): 046103. doi: 10.1088/1674-1137/40/4/046103

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Received: 2015-07-22

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Supported by National Natural Science Foundation of China(11079045, 11179003 and 11305233)}

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通讯作者: 陈斌, [email protected]

1.
沈阳化工大学材料科学与工程学院沈阳 110142

Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs

Corresponding author: Hong Su,

1. Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China

2. University of Chinese Academy of Sciences, Beijing 100049, China

3. Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou 730000, China

4. Science and Technology on Reliability Physics and Application of Electronic Component Laboratory, China Electronic Product Reliability and Environmental Testing Research Institute, Guangzhou 510610, China

Received Date: 2015-07-22

Available Online: 2016-03-28

Fund Project: Supported by National Natural Science Foundation of China(11079045, 11179003 and 11305233)}

Abstract: Embedded RAM blocks(BRAMs) in field programmable gate arrays(FPGAs) are susceptible to single event effects(SEEs) induced by environmental factors such as cosmic rays, heavy ions, alpha particles and so on. As technology scales, the issue will be more serious. In order to tackle this issue, two different error correcting codes(ECCs), the shortened Hamming codes and shortened BCH codes, are investigated in this paper. The concrete design methods of the codes are presented. Also, the codes are both implemented in flash-based FPGAs. Finally, the synthesis report and simulation results are presented in the paper. Moreover, heavy-ion experiments are performed, and the experimental results indicate that the error cross-section of the device using the shortened Hamming codes can be reduced by two orders of magnitude compared with the device without mitigation, and no errors are discovered in the experiments for the device using the shortened BCH codes.

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Implementation and verification of different ECC mitigation designs for BRAMs in flash-based FPGAs

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